In computer system cache memory designs, a cache is addressed using lower-order bits of the physical address while the higher-order bits are stored in a tag field, since the size of the cache is a small fraction of the size of the entire physical address space of the system. During a memory reference, a cache line's tag is compared against the memory reference's address to determine whether the memory reference is a cache hit. As the size of caches grows, the number of cache lines expands correspondingly, and the tag storage for these cache lines increases proportionately. For example, as conventional caches increase in size to multiple gigabytes, the associated cache tags can potentially occupy hundreds of megabytes. To reduce cache tag-matching latency, it is useful to locate these cache tags on a processor chip. However, it may not be cost effective to store hundreds of megabytes of cache tags on-chip. On the other hand, storing the cache tags off-chip introduces additional latency for tag lookups and also consumes valuable bandwidth.